(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate both logic and embedded dynamic random access memory, (DRAM), devices, on the same semiconductor substrate, featuring a self-aligned metal silicide, (salicide), layer, formed on the gate structures for both the logic and embedded DRAM devices, while only formed on the source/drain regions of the logic devices.
(2) Description of Prior Art
To decrease the resistance of word lines, for logic devices as well as for DRAM devices, a salicide layer is employed on an underlying polysilicon gate structure. The same salicide layer is also used on the source/drain regions of logic devices, again to increase the conductivity of these elements. However for reliability reasons salicide layers are not used on source/drain regions of DRAM devices. Therefore to reduce cost and process complexity, process sequences have been generated in which both logic and embedded DRAM devices are simultaneously formed on the same semiconductor chip, featuring salicided gate structures and salicided source/drain regions for logic devices, but forming salicide only on the gate structures of the embedded DRAM devices.
Prior art, such as Sung, in U.S. Pat. No. 5,858,831, do show salicide formation on the source/drain regions of logic devices and an absence of salicide on the DRAM source/drain regions. However that prior art does not form a salicide layer on the gate structure, but forms polycide, (metal silicide--polysilicon), gate structures for both logic and DRAM devices, prior to forming a salicide layer on the source/drain region of the logic device. This present invention will describe a process sequence for simultaneous fabrication of both logic devices and embedded DRAM devices, in which salicide layers are simultaneously formed on the gate structures of both device types, but on only the source/drain region of the logic devices, thus presenting the desired performance increase for the logic devices, offered by the salicided source/drain regions, while preventing reliability concerns for the DRAM devices by blocking the salicide formation on the DRAM source/drain regions.